1. Field of the Invention
The present invention is concerned with the field of power electronics. It relates to a method for the production of a MOS-controlled power semiconductor component, which power semiconductor component comprises, in a common substrate, a plurality of component cells which are arranged next to one another and are connected in parallel, a bipolar transistor formed by a collector region of a first conductivity type, a superior base region of a second conductivity type and an emitter region of the first conductivity type, which emitter region is incorporated from above into the base region, being present in each component cell, and a MOS channel structure for controlling the bipolar transistor being provided on the emitter side, which MOS channel structure comprises a source region of the second conductivity type, which source region lies above the emitter region, a channel region of the first conductivity type, which channel region is arranged on the edge side of the emitter region between the source region and the base region, and a gate electrode which is arranged in an insulated manner above the channel region.
2. Discussion of Background
Today's MOS-controlled power semiconductor components of the IGBT type (Insulated Gate Bipolar Transistors) comprise a multiplicity of identical component cells which are connected in parallel and are accommodated next to one another in a common semiconductor substrate. A bipolar transistor is component cells of such a power semiconductor component 1, one of which is represented in cross-section in FIG. 1 by way of example, which bipolar transistor comprises a (P.sup.+ -doped) collector region 4, an (N-doped) base region 3 and a (P.sup.+ -doped) emitter region 6. On the emitter side of the IGBT, a MOS channel structure of the cell, which comprises a (P-doped) channel region 7, an (N.sup.+ -doped) source region 8 and a (polysilicon) gate electrode 9 arranged in an insulated manner above the channel region 7, is used to control the base current of the integrated bipolar transistor.
For this purpose, the channel region 7 connects the source region 8 to the base region 3, that is to say to the base of the bipolar transistor. The base region 3 is part of a continuous base layer. The collector region 4 is part of a continuous collector layer. The gate electrode 9 is insulated by an oxide 10 from the inferior substrate 2 and the superior metallization layer of the emitter contact 11. The emitter contact simultaneously makes contact with the emitter region 6 and the source region 8. A collector metallization layer 5 is provided on the underside of the substrate 2 in order to make contact with the IGBT on the collector side.
The lateral extent of the component cells may follow different geometries. Two examples of cell geometries known and employed today are represented in a plan view from above in FIG. 2(a) and (b). FIG. 2(a) shows a strip structure with an elongate emitter region 6, on the two long sides of which two source regions 8 in strip form are superposed and which is surrounded entirely by the gate electrode 9. FIG. 2(b) shows a polygonal (in this case hexagonal) cell structure, in which a central polygonal emitter region 6' is covered on the edge side by a continuous, annular source region 8' and is enclosed by a gate electrode 9'. The emitter contact has been omitted in both examples.
One problem that arises with an IGBT is the so-called latch-up strength of the components: if the hole current of the bipolar transistor is too high, the parasitic thyristor formed by the source region 8, the emitter region 6, the base region 3 and the collector region 4 may be triggered. Furthermore, in the event of a short circuit, the power density in the region of the MOS channel structure may become so high that thermal destruction of the component occurs. It is therefore fundamentally desirable to limit the short-circuit current (power limiting in the event of a short circuit) and, in addition, to keep the hole bypass resistance around the source region 8 as small as possible (reduction in the latch-up sensitivity). These measures should be achieved with minimum additional outlay in terms of process technology (costs).
Nowadays, uniform source regions are used in a number of IGBTs, which means that a mask is saved: the (N.sup.+ -type) source regions are implanted without a mask. The implantation is masked by a thick oxide outside the active component area. During contact hole etching, etching into the topmost silicon layer is then additionally effected and the N.sup.+ -type layer is removed again. This produces a lateral contact to the source region at the edge of the contact hole window.
Such maskless source region implantation is represented in FIGS. 3 and 4 in a cross-section through a component cell of a power semiconductor component 12: in the case of this component, a collector region (a collector layer) 15 is initially introduced from underneath into the N-doped substrate 13, which simultaneously forms the base region 14. An emitter region 17 and the channel regions 18 are furthermore introduced from above--through a window 21 and masked by the subsequent gate electrode 19. A source region 22 is then implanted, masked by the gate electrode 19, the central region of which source region is etched away in order to produce a contact hole 23 (FIG. 4). Through the contact hole 23, an emitter contact 24 makes contact both with the emitter region 17 and the source regions 22. Contact is made on the collector side by means of a collector metallization layer 16.
The disadvantage of this technology is that the N.sup.+ -type layer or the source region 22 is not structured along the edge of the polysilicon gate electrode, that is to say along the edge of the contact hole 23. This results in a large channel width (region over which the channel is effective) for the MOS channel structure, whereby the power density per IGBT cell becomes very large in the event of a short circuit.
In the case of other known types of IGBT, a separate photoresist mask is used for the implantation of the source region 22. Such a mask 25, of the kind suitable for a cell geometry according to FIG. 2(a), is represented as a detail in a plan view in FIG. 5(a). Small mask openings 26 are provided in two rows in this mask 25, through which openings the N.sup.+ implantation is carried out. The resulting cell structure has--in comparison with FIG. 2(a)--the arrangement of gate region 27, emitter region 28 and insular source regions 29 that is shown in FIG. 5(b). This makes it possible, although at the cost of increasing process complexity, to set the channel width and thus the power density in the event of a short circuit by design (above all of the source regions). A further advantage of this method is that the lateral limiting of the N.sup.+ -type source region creates a hole bypass which reduces the latch-up sensitivity of the component. As already mentioned, however, this solution requires at least one additional mask step, which undesirably complicates the production process.